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» Validation coverage analysis for complex digital designs
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ICCAD
1996
IEEE
144views Hardware» more  ICCAD 1996»
13 years 9 months ago
Validation coverage analysis for complex digital designs
The functional validation of a state-of-the-art digital design is usually performed by simulation of a register-transfer-level model. The degree to which the testvector suite cove...
Richard C. Ho, Mark Horowitz
TC
1998
13 years 4 months ago
Abstraction Techniques for Validation Coverage Analysis and Test Generation
ion Techniques for Validation Coverage Analysis and Test Generation Dinos Moundanos, Jacob A. Abraham, Fellow, IEEE, and Yatin V. Hoskote —The enormous state spaces which must be...
Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Ho...
ASPDAC
2012
ACM
265views Hardware» more  ASPDAC 2012»
12 years 17 days ago
Improving validation coverage metrics to account for limited observability
—In both pre-silicon and post-silicon validation, the detection of design errors requires both stimulus capable of activating the errors and checkers capable of detecting the beh...
Peter Lisherness, Kwang-Ting Cheng
DATE
2006
IEEE
143views Hardware» more  DATE 2006»
13 years 11 months ago
A coverage metric for the validation of interacting processes
We present a coverage metric which evaluates the testing of a set of interacting concurrent processes. Existing behavioral coverage metrics focus almost exclusively on the testing...
Ian G. Harris
ISVLSI
2007
IEEE
181views VLSI» more  ISVLSI 2007»
13 years 11 months ago
Code-coverage Based Test Vector Generation for SystemC Designs
Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity in...
Alair Dias Jr., Diógenes Cecilio da Silva J...