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ISSS
2002
IEEE
127views Hardware» more  ISSS 2002»
13 years 10 months ago
Validation in a Component-Based Design Flow for Multicore SoCs
Currently, since many SoCs include heterogeneous components such as CPUs, DSPs, ASICs, memories, buses, etc., system integration becomes a major step in the design flow. To enable...
Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima,...
AHS
2007
IEEE
239views Hardware» more  AHS 2007»
13 years 9 months ago
Separation of Data flow and Control flow in Reconfigurable Multi-core SoCs using the Gannet Service-based Architecture
This paper presents a mechanism for the separation of control and data flow in NoC-based SoCs consisting of multiple heterogeneous reconfigurable IP cores. This mechanism enables ...
Wim Vanderbauwhede
DAC
2007
ACM
14 years 6 months ago
Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
Ümit Y. Ogras, Diana Marculescu, Puru Choudha...
IESS
2007
Springer
120views Hardware» more  IESS 2007»
13 years 11 months ago
Error Containment in the Time-Triggered System-On-a-Chip Architecture
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...
NOCS
2009
IEEE
13 years 11 months ago
CTC: An end-to-end flow control protocol for multi-core systems-on-chip
We propose Connection then Credits (CTC) as a new end-to-end flow control protocol to handle messagedependent deadlocks in networks-on-chip (NoC) for multicore systems-on-chip. C...
Nicola Concer, Luciano Bononi, Michael Soulie, Ric...