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» Variation Aware Placement for FPGAs
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FPL
2006
Springer
137views Hardware» more  FPL 2006»
13 years 8 months ago
FPGA Performance Optimization Via Chipwise Placement Considering Process Variations
Both custom IC and FPGA designs in the nanometer regime suffer from process variations. But different from custom ICs, FPGAs' programmability offers a unique design freedom t...
Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton
ISVLSI
2006
IEEE
85views VLSI» more  ISVLSI 2006»
13 years 10 months ago
Variation Aware Placement for FPGAs
Suresh Srinivasan, Narayanan Vijaykrishnan
ICCAD
2001
IEEE
103views Hardware» more  ICCAD 2001»
14 years 1 months ago
Interconnect Resource-Aware Placement for Hierarchical FPGAs
In this paper, we utilize Rent’s rule as an empirical measure for efficient clustering and placement of circuits on hierarchical FPGAs. We show that careful matching of design c...
Amit Singh, Ganapathy Parthasarathy, Malgorzata Ma...
IPPS
2007
IEEE
13 years 11 months ago
Miss Ratio Improvement For Real-Time Applications Using Fragmentation-Aware Placement
Partially reconfigurable Field-Programmable Gate Arrays (FPGAs) allow parts of the chip to be configured at run-time where each part could hold an independent task. Online place...
Ahmed Abou ElFarag, Hatem M. El-Boghdadi, Samir I....
FPL
2007
Springer
100views Hardware» more  FPL 2007»
13 years 11 months ago
Clock-Aware Placement for FPGAs
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of powe...
Julien Lamoureux, Steven J. E. Wilton