5 search results - page 1 / 1 » Variational interconnect analysis via PMTBR |
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
We demonstrate an algorithmfor interconnect modeling in rhe presence ofprocess variation based on extension of the truncated balanced realizationmodel reduction algorithmto multi-...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
Abstract-- This paper describes the stochastic model order reduction algorithm via stochastic Hermite Polynomials from the practical implementation perspective. Comparing with exis...
ICCAD
2007
IEEE
14 years 2 months ago
2007
IEEE
— Clock meshes posses inherent low clock skews and excellent immunity to PVT variations, and have increasingly found their way to high-performance IC designs. However, analysis o...
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
Process variations in modern VLSI technologies are growing in both magnitude and dimensionality. To assess performance variability, complex simulation and performance models param...
3DIC
2009
IEEE
14 years 4 days ago
2009
IEEE
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...