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    » Vdd programmability to reduce FPGA interconnect power
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    DAC
    2004
    ACM
    154views Computer Architecture» more  DAC 2004»
    FPGA power reduction using configurable dual-Vdd
    14 years 6 months ago
    FPGA power reduction using configurable dual-Vdd
    Download  www.ee.ucla.edu
    Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
    Fei Li, Yan Lin, Lei He
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    TODAES
    2008
    69views more  TODAES 2008»
    Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
    13 years 5 months ago
    Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
    Download  www.ee.ucla.edu
    Yu Hu, Yan Lin, Lei He, Tim Tuan
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    DAC
    2005
    ACM
    109views Computer Architecture» more  DAC 2005»
    Device and architecture co-optimization for FPGA power reduction
    14 years 6 months ago
    Device and architecture co-optimization for FPGA power reduction
    Download  www.ee.ucla.edu
    Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
    Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
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    ICCAD
    2004
    IEEE
    95views Hardware» more  ICCAD 2004»
    Low-power programmable routing circuitry for FPGAs
    14 years 2 months ago
    Low-power programmable routing circuitry for FPGAs
    Download  www.eecg.toronto.edu
    We propose two new FPGA routing switch designs that are programmable to operate in three different modes: highspeed, low-power or sleep. High-speed mode provides similar power an...
    Jason Helge Anderson, Farid N. Najm
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    ISLPED
    2005
    ACM
    96views Hardware» more  ISLPED 2005»
    Power-optimal repeater insertion considering Vdd and Vth as design freedoms
    13 years 11 months ago
    Power-optimal repeater insertion considering Vdd and Vth as design freedoms
    Download  www.cecs.uci.edu
    This work first presents an analytical repeater insertion method which optimizes power under delay constraint for a single net. This method finds the optimal repeater insertion ...
    Yu Ching Chang, King Ho Tam, Lei He
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