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ICPP
2006
IEEE
13 years 11 months ago
Vector Lane Threading
Multi-lane vector processors achieve excellent computational throughput for programs with high data-level parallelism (DLP). However, application phases without significant DLP ar...
Suzanne Rivoire, Rebecca Schultz, Tomofumi Okuda, ...
AISS
2010
169views more  AISS 2010»
13 years 2 months ago
Effective Lane Detection and Tracking Method Using Statistical Modeling of Color and Lane Edge-orientation
This paper proposes an effective lane detection and tracking method using statistical modeling of lane color and edge-orientation in the image sequence. At first, we will address ...
Jin-Wook Lee, Jae-Soo Cho
CATA
2004
13 years 6 months ago
The Instruction Execution Mechanism for Responsive Multithreaded Processor
This paper describes the instruction execution mechanism of Responsive Multithreaded (RMT) Processor for distributed real-time processing. The execution order of each thread is co...
Tstomu Itou, Nobuyuki Yamasaki
ISCA
2012
IEEE
218views Hardware» more  ISCA 2012»
11 years 7 months ago
CAPRI: Prediction of compaction-adequacy for handling control-divergence in GPGPU architectures
Wide SIMD-based GPUs have evolved into a promising platform for running general purpose workloads. Current programmable GPUs allow even code with irregular control to execute well...
Minsoo Rhu, Mattan Erez
ASAP
2005
IEEE
182views Hardware» more  ASAP 2005»
13 years 11 months ago
A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor
We studied the dynamic instruction count reduction for a single-thread, vectorized and a multi-threaded, non-vectorized, MPEG-4 video encoder. Results indicate a maximum improveme...
Tom R. Jacobs, José L. Núñez-...