Sciweavers

47 search results - page 2 / 10
» Vector Lane Threading
Sort
View
MFCS
1990
Springer
13 years 9 months ago
On Checking Versus Evaluation of Multiple Queries
The plausibility of computing the answers to many membership queries to a hard set with few queries is the subject of the theory of terseness. In this paper, we develop companion ...
William I. Gasarch, Lane A. Hemachandra, Albrecht ...
CASES
2009
ACM
14 years 8 days ago
Fine-grain performance scaling of soft vector processors
Embedded systems are often implemented on FPGA devices and 25% of the time [2] include a soft processor— a processor built using the FPGA reprogrammable fabric. Because of their...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
FPGA
2008
ACM
133views FPGA» more  FPGA 2008»
13 years 7 months ago
Vector processing as a soft-core CPU accelerator
The currently accepted method of accelerating applications in FPGA soft processor systems is to design a custom hardware accelerator. This paper suggests the alternative approach ...
Jason Yu, Guy Lemieux, Christopher Eagleston
CIE
2005
Springer
13 years 11 months ago
A Thread Algebra with Multi-level Strategic Interleaving
In a previous paper, we developed an algebraic theory of threads and multi-threads based on strategic interleaving. This theory includes a number of plausible interleaving strategi...
Jan A. Bergstra, C. A. Middelburg
ACMSE
2009
ACM
14 years 8 days ago
Bit vector algorithms enabling high-speed and memory-efficient firewall blacklisting
In a world of increasing Internet connectivity coupled with increasing computer security risks, security conscious network applications implementing blacklisting technology are be...
J. Lane Thames, Randal Abler, David Keeling