37 search results - page 1 / 8 » Verification of Floating-Point Adders |
CAV
1998
Springer
13 years 9 months ago
1998
Springer
DFT
2009
IEEE
13 years 8 months ago
2009
IEEE
We present an error detection technique for a floating point adder which uses a checker adder of reduced precision to determine if the result is correct within some error bound. O...
ARITH
2009
IEEE
14 years 2 days ago
2009
IEEE
The design of a component to perform parallel addition of multiple floating-point (FP) operands is explored in this work. In particular, a 3-input FP adder is discussed in more d...
FMCAD
2000
Springer
13 years 8 months ago
2000
Springer
Abstract. We have formal verified a number of algorithms for evaluating transcendental functions in double-extended precision floating point arithmetic in the Intel
ARITH
1999
IEEE
13 years 9 months ago
1999
IEEE
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...