6 search results - page 1 / 2 » Verification of Pipelined Microprocessors by Comparing Memor... |
ASIAN
1997
Springer
13 years 8 months ago
1997
Springer
ACSD
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper makes the idea of memory shadowing [5] applicable to symbolic ternary simulation. Memory shadowing, an extension of Burch and Dill's pipeline verification method [...
DAC
1994
ACM
13 years 9 months ago
1994
ACM
Abstract - We address the problem of automatically verifying large digital designs at the logic level, against high-level specifications. In this paper, we present a methodology wh...
TACAS
1998
Springer
13 years 9 months ago
1998
Springer
This paper enables symbolic ternary simulation of systems with large embedded memories. Each memory array is replaced with a behavioral model, where the number of symbolic variable...
ISCA
2002
IEEE
13 years 9 months ago
2002
IEEE
The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations...