399 search results - page 1 / 80 » Verification of System Level Model Transformations |
IJPP
2006
13 years 5 months ago
2006
ICCD
2000
IEEE
13 years 9 months ago
2000
IEEE
A major obstacle to widespread acceptance of formal verification is the difficulty in using the tools effectively. Although learning the basic syntax and operation of a formal ver...
DAC
2006
ACM
13 years 11 months ago
2006
ACM
This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are bei...
TCAD
2008
13 years 5 months ago
2008
Due to the increasing abstraction gap between the initial system model and a final implementation, the verification of the respective models against each other is a formidable task...
CL
2010
Springer
13 years 5 months ago
2010
Springer
In this paper we present the syntax, semantics, and compilation of a new system-level programming language called SystemJ. SystemJ is a multiclock language supporting the Globally...