196 search results - page 1 / 40 » Verification of timing Properties of VHDL |
CAV
1993
Springer
13 years 9 months ago
1993
Springer
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
With VHDL models increasing their size, it becomes more important to assure the quality of these descriptions in order to improve simulation performances, to make project maintain...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
This paper describes the verification of two versions of a bridge between two on-chip buses. The verification was performed just as the Infineon Technologies Design Centre in Bris...