138 search results - page 2 / 28 » Very Compact FPGA Implementation of the AES Algorithm |
JUCS
2007
13 years 4 months ago
2007
: This article presents an architecture that encrypts data with the AES algorithm. This architecture can be implemented on the Xilinx Virtex II FPGA family, by applying pipelining ...
FPL
2003
Springer
13 years 10 months ago
2003
Springer
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
FPGA
2000
ACM
13 years 8 months ago
2000
ACM
With the expiration of the Data Encryption Standard (DES) in 1998, the Advanced Encryption Standard (AES) development process is well underway. It is hoped that the result of the ...
CSI
2011
12 years 11 months ago
2011
Offline processing of acoustic emission (AE) signal waveforms recorded during a long-term AE monitoring session is a challenging problem in AE testing area. This is due to the fac...
GLVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...