138 search results - page 3 / 28 » Very Compact FPGA Implementation of the AES Algorithm |
RECONFIG
2008
IEEE
13 years 11 months ago
2008
IEEE
1 We present a fast, efficient, and parameterized modular multiplier and a secure exponentiation circuit especially intended for FPGAs on the low end of the price range. The desig...
FPL
2011
Springer
12 years 5 months ago
2011
Springer
In this paper two compact hardware structures for the computation of the CLEFIA encryption algorithm are presented. One structure based on the existing state of the art and a nove...
FDTC
2009
Springer
13 years 12 months ago
2009
Springer
—In order to protect crypto-systems against side channel attacks various countermeasures have been implemented such as dual-rail logic or masking. Faults attacks are a powerful t...
DAC
2001
ACM
14 years 6 months ago
2001
ACM
: Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concu...
ESANN
2006
13 years 6 months ago
2006
Abstract. Current digital, directly mapped implementations of spiking neural networks use serial processing and parallel arithmetic. On a standard CPU, this might be the good choic...