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» Virtual channels in networks on chip: implementation and eva...
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SBCCI
2005
ACM
123views VLSI» more  SBCCI 2005»
13 years 10 months ago
Fault tolerance overhead in network-on-chip flow control schemes
Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet propagation across the network and for low idling of network resources. Buffer manageme...
Antonio Pullini, Federico Angiolini, Davide Bertoz...
SC
2009
ACM
13 years 11 months ago
Allocator implementations for network-on-chip routers
The present contribution explores the design space for virtual channel (VC) and switch allocators in network-on-chip (NoC) routers. Based on detailed RTL-level implementations, we...
Daniel U. Becker, William J. Dally
DATE
2008
IEEE
145views Hardware» more  DATE 2008»
13 years 11 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
ISVLSI
2006
IEEE
129views VLSI» more  ISVLSI 2006»
13 years 11 months ago
Connection-oriented Multicasting in Wormhole-switched Networks on Chip
Network-on-Chip (NoC) proposes networks to replace buses as a scalable global communication interconnect for future SoC designs. However, a bus is very efficient in broadcasting....
Zhonghai Lu, Bei Yin, Axel Jantsch
ICCD
2006
IEEE
137views Hardware» more  ICCD 2006»
14 years 1 months ago
Implementation and Evaluation of On-Chip Network Architectures
— Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has evolved from proprietary busses to networked architectures. A similar evolution is o...
Paul Gratz, Changkyu Kim, Robert G. McDonald, Step...