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SIGGRAPH
2000
ACM
13 years 10 months ago
Pomegranate: a fully scalable graphics architecture
Pomegranate is a parallel hardware architecture for polygon rendering that provides scalable input bandwidth, triangle rate, pixel rate, texture memory and display bandwidth while...
Matthew Eldridge, Homan Igehy, Pat Hanrahan
EUROMICRO
1999
IEEE
13 years 10 months ago
Enhancing Security in the Memory Management Unit
We propose an hardware solution to several security problems that are difficult to solve on classical processor architectures, like licensing, electronic commerce, or software pri...
Tanguy Gilmont, Jean-Didier Legat, Jean-Jacques Qu...
WOMPAT
2001
Springer
13 years 10 months ago
CableS : Thread Control and Memory System Extensions for Shared Virtual Memory Clusters
Clusters of high-end workstations and PCs are currently used in many application domains to perform large-scale computations or as scalable servers for I/O bound tasks. Although cl...
Peter Jamieson, Angelos Bilas
EUROPAR
2010
Springer
13 years 6 months ago
Optimized On-Chip-Pipelined Mergesort on the Cell/B.E
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...
Rikard Hultén, Christoph W. Kessler, Jö...
FPL
2004
Springer
95views Hardware» more  FPL 2004»
13 years 11 months ago
Increasing Pipelined IP Core Utilization in Process Networks Using Exploration
At Leiden Embedded Research Center, we are building a tool chain called Compaan/Laura that allows us to do fast mapping of applications written in Matlab onto reconfigurable platf...
Claudiu Zissulescu, Bart Kienhuis, Ed F. Depretter...