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FPGA
2010
ACM
191views FPGA» more  FPGA 2010»
13 years 11 months ago
Voter insertion algorithms for FPGA designs using triple modular redundancy
Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems t...
Jonathan M. Johnson, Michael J. Wirthlin
DATE
2005
IEEE
128views Hardware» more  DATE 2005»
13 years 10 months ago
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected b...
Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Ca...
VTS
2000
IEEE
95views Hardware» more  VTS 2000»
13 years 9 months ago
Word Voter: A New Voter Design for Triple Modular Redundant Systems
Redundancy techniques are commonly used to design dependable systems to ensure high reliability, availability and data integrity. Triple Modular Redundancy (TMR) is a widely used ...
Subhasish Mitra, Edward J. McCluskey
CODES
2008
IEEE
13 years 11 months ago
Symbolic voter placement for dependability-aware system synthesis
This paper presents a system synthesis approach for dependable embedded systems. The proposed approach significantly extends previous work by automatically inserting fault detect...
Felix Reimann, Michael Glabeta, Martin Lukasiewycz...
ICPR
2004
IEEE
14 years 6 months ago
From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers
Parallel processors such as SIMD computers have been successfully used in various areas of high performance image and data processing. Due to their characteristics of highly regula...
Jie Han, Pieter Jonker