Sciweavers

14 search results - page 3 / 3
» WTA: waveform-based timing analysis for deep submicron circu...
Sort
View
ICCD
2003
IEEE
134views Hardware» more  ICCD 2003»
14 years 1 months ago
An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk
Analyzing the effect of crosstalk on delay is critical for high performance circuits. The major bottleneck in performing crosstalkinduced delay analysis is the high computational ...
Venkatesan Rajappan, Sachin S. Sapatnekar
ICCAD
2005
IEEE
168views Hardware» more  ICCAD 2005»
14 years 1 months ago
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
— Process variations cause significant timing uncertainty and yield degradation in deep sub-micron technologies. A solution to counter timing uncertainty is post-silicon clock t...
Jeng-Liang Tsai, Lizheng Zhang
ICCAD
2001
IEEE
100views Hardware» more  ICCAD 2001»
14 years 1 months ago
Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets
In deep submicron VLSI circuits, interconnect reliability due to electromigration and thermal effects is fast becoming a serious design issue particularly for long signal lines. T...
Kaustav Banerjee, Amit Mehrotra
ICCAD
2003
IEEE
175views Hardware» more  ICCAD 2003»
14 years 1 months ago
Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
Abhishek Singh, Jitin Tharian, Jim Plusquellic