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» Weaving Relations for Cache Performance
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IEEEPACT
2009
IEEE
13 years 3 months ago
Cache Sharing Management for Performance Fairness in Chip Multiprocessors
Resource sharing can cause unfair and unpredictable performance of concurrently executing applications in Chip-Multiprocessors (CMP). The shared last-level cache is one of the mos...
Xing Zhou, Wenguang Chen, Weimin Zheng
MICRO
1997
IEEE
110views Hardware» more  MICRO 1997»
13 years 9 months ago
The Design and Performance of a Conflict-Avoiding Cache
High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected i...
Nigel P. Topham, Antonio González, Jos&eacu...
SC
2000
ACM
13 years 9 months ago
Using Hardware Performance Monitors to Isolate Memory Bottlenecks
In this paper, we present and evaluate two techniques that use different styles of hardware support to provide data structure specific processor cache information. In one approach...
Bryan R. Buck, Jeffrey K. Hollingsworth
PDIS
1994
IEEE
13 years 9 months ago
A Predicate-based Caching Scheme for Client-Server Database Architectures
We propose a new client-side data-caching scheme for relational databases with a central server and multiple clients. Data are loaded into each client cache based on queries execut...
Arthur M. Keller, Julie Basu
MICRO
2006
IEEE
96views Hardware» more  MICRO 2006»
13 years 5 months ago
Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions
CMPs enable simultaneous execution of multiple applications on the same platforms that share cache resources. Diversity in the cache access patterns of these simultaneously execut...
Keshavan Varadarajan, S. K. Nandy, Vishal Sharda, ...