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» Whirlpool PLAs: a regular logic structure and their synthesi...
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DSD
2006
IEEE
113views Hardware» more  DSD 2006»
13 years 11 months ago
An Asynchronous PLA with Improved Security Characteristics
Programmable logic arrays (PLAs) present an alternative to logic-gate based design. We propose the transistor level structure of a PLA for single-rail asynchronous applications. T...
Petros Oikonomakos, Simon W. Moore
GLVLSI
2007
IEEE
140views VLSI» more  GLVLSI 2007»
13 years 11 months ago
Structured and tuned array generation (STAG) for high-performance random logic
Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides...
Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kos...
DELTA
2006
IEEE
13 years 9 months ago
Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays
The difficulties of designing nanoscale circuits include the need for regular circuit structure and controlling the timing requirements. A cellular array has highly regular struct...
Jia Di, Dilip P. Vasudevan
ICCS
2005
Springer
13 years 10 months ago
A Logarithmic Time Method for Two's Complementation
This paper proposes an innovative algorithm to find the two’s complement of a binary number. The proposed method works in logarithmic time (O(logN)) instead of the worst case li...
Jung-Yup Kang, Jean-Luc Gaudiot
FPGA
1992
ACM
176views FPGA» more  FPGA 1992»
13 years 9 months ago
Minimization of Permuted Reed-Muller Trees for Cellular Logic
The new family of Field Programmable Gate Arrays, CLI6000 from Concurrent Logic Inc realizes the truly Cellular Logic. It has been mainly designed for the realization of data path...
Li-Fei Wu, Marek A. Perkowski