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» WireMap: FPGA technology mapping for improved routability
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ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
14 years 2 months ago
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
Yu Hu, Satyaki Das, Steven Trimberger, Lei He
GLVLSI
2009
IEEE
189views VLSI» more  GLVLSI 2009»
14 years 15 days ago
High-performance, cost-effective heterogeneous 3D FPGA architectures
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...
Roto Le, Sherief Reda, R. Iris Bahar
DATE
2008
IEEE
143views Hardware» more  DATE 2008»
14 years 6 days ago
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming
Multi-input addition is an important operation for many DSP and video processing applications. On FPGAs, multi-input addition has traditionally been implemented using trees of car...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
FCCM
2002
IEEE
174views VLSI» more  FCCM 2002»
13 years 10 months ago
PAM-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs
This paper explores the implications of integrating flexible module generation into a compiler for FPGAs. The objective is to improve the programmabilityof FPGAs, or in other wor...
Oskar Mencer
FPGA
2007
ACM
124views FPGA» more  FPGA 2007»
13 years 12 months ago
A practical FPGA-based framework for novel CMP research
Chip-multiprocessors are quickly gaining momentum in all segments of computing. However, the practical success of CMPs strongly depends on addressing the difficulty of multithread...
Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy T...