16 search results - page 2 / 4 » Wrapper Design for the Reuse of Networks-on-Chip as Test Acc... |
ICCD
2005
IEEE
14 years 2 months ago
2005
IEEE
The manufacturing test cost for mixed-signal SOCs is widely recognized to be much higher than that for digital SOCs. It has been shown in recent prior work that the use of analog ...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Existing work on testing NoC-based systems advocates to reuse the on-chip network itself as test access mechanism (TAM) to transport test data to/from embedded cores. While this m...
VTS
2002
IEEE
13 years 10 months ago
2002
IEEE
The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM). Wrapper/TAM co-optimization is ther...
ITC
1998
IEEE
13 years 9 months ago
1998
IEEE
The main objective of core-based IC design is improvement of design efficiency and time-to-market. In order to prevent test development from becoming the bottleneck in the entire ...
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...