16 search results - page 3 / 4 » Wrapper Design for the Reuse of Networks-on-Chip as Test Acc... |
DATE
2006
IEEE
13 years 12 months ago
2006
IEEE
This paper presents a wrapper and test access mechanism design for multi-clock domain SoCs that consists of cores with different clock frequencies during test. We also propose a t...
DATE
2003
IEEE
13 years 11 months ago
2003
IEEE
One of the difficult problems which core-based systemon-chip (SoC) designs face is test access. For testing the cores in a SoC, a special mechanism is required, since they are no...
ISVLSI
2008
IEEE
14 years 5 days ago
2008
IEEE
Re-using the network in a NoC-based system as a test access mechanism is an attractive solution as pointed out by several authors. As a consequence, testing of NoC-based SoCs is b...
DFT
2006
IEEE
13 years 12 months ago
2006
IEEE
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
ICCAD
2000
IEEE
13 years 10 months ago
2000
IEEE
Spurred by technology leading to the availability of millions of gates per chip, system-level integration is evolving as a new paradigm, allowing entire systems to be built on a s...