1000 search results - page 1 / 200 » Yield-Aware Cache Architectures |
MICRO
2006
IEEE
13 years 10 months ago
2006
IEEE
One of the major issues faced by the semiconductor industry today is that of reducing chip yields. As the process technologies have scaled to smaller feature sizes, chip yields ha...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
Timing margin (slack) needs to be carefully managed to ensure a satisfactory timing yield. We propose a new design flow that combines a false-path-aware gate sizing and a statisti...
CN
1998
13 years 4 months ago
1998
This paper describes the architecture of Network Appliance’s NetCache proxy cache. It discusses sizing proxy caches, contrasts the advantages and disadvantages of transparent ca...
EUROPAR
2010
Springer
13 years 6 months ago
2010
Springer
Abstract. Shared last level cache is crucial to performance. However, multithread program model incurs serious contention in shared cache. In this paper, to reduce average cache ac...
ISCAPDCS
2004
13 years 6 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...