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ARCS
1997
Springer
13 years 9 months ago
Kapselung mobiler Programme
Lars Reuther, Hermann Härtig
ISSS
1997
IEEE
102views Hardware» more  ISSS 1997»
13 years 9 months ago
An Efficient Model for DSP Code Generation: Performance, Code Size, Estimated Energy
This paper presents a model for simultaneous instruction selection, compaction, and register allocation. An arc mapping model along with logical propositions is used to create an ...
Catherine H. Gebotys
ARCS
1997
Springer
13 years 9 months ago
Hardware-Supported Fault Tolerance for Multiprocessors
To provide a computing system to be dependable fault tolerance mechanisms have to be included. Especially massive parallelism represents a new challenge for fault tolerance. In th...
Mario Dal Cin, Wolfgang Hohl, Volkmar Sieh
ARCS
1997
Springer
13 years 9 months ago
A RISC Processor with Extended Forwarding
The paper examines a simple conceptual modification of the operation unit of a RISC processor. We propose to substitute a part of the conventional general purpose register file by...
Gert Markwardt, Günter Kemnitz, Rainer G. Spa...
ARCS
1997
Springer
13 years 9 months ago
A Novel Universal Sequencer Hardware
This paper introduces a powerful novel sequencer hardware for controlling computational machines and for structured DMA (direct memory access) applications. The paper introduces t...
Reiner W. Hartenstein, Jürgen Becker, Michael...