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2000
13 years 5 months ago
Experimental performance evaluation of batch means procedures for simulation output analysis
We summarize the results of an extensive experimental performance evaluation of selected batch means procedures for building a confidence interval for a steady-state expected simu...
Natalie M. Steiger, James R. Wilson
ASAP
2000
IEEE
125views Hardware» more  ASAP 2000»
13 years 9 months ago
High Level Modeling for Parallel Executions of Nested Loop Algorithms
High level modeling and (quantitative) performance analysis of signal processing systems requires high level models for the applications(algorithms) and the implementations (archi...
Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, B...
ASAP
2000
IEEE
121views Hardware» more  ASAP 2000»
13 years 9 months ago
A Hardware Algorithm for Variable-Precision Logarithm
This paper presents an e cient hardware algorithm for variable-precision logarithm. The algorithm uses an iterative te chnique that employs table lookups and polynomial approximat...
Javier Hormigo, Julio Villalba, Michael J. Schulte
ASAP
2000
IEEE
142views Hardware» more  ASAP 2000»
13 years 9 months ago
Contention-Conscious Transaction Ordering in Embedded Multiprocessors
This paper explores the problem of efficiently ordering interprocessor communication operations in statically-scheduled multiprocessors for iterative dataflow graphs. In most digi...
Mukul Khandelia, Shuvra S. Bhattacharyya
ASAP
2000
IEEE
184views Hardware» more  ASAP 2000»
13 years 9 months ago
Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter
Sorting long sequences of keys is a problem that occurs in many different applications. For embedded systems, a uniprocessor software solution is often not applicable due to the l...
Marcus Bednara, Oliver Beyer, Jürgen Teich, R...