39 search results - page 7 / 8 » asap 2007 |
ASAP
2007
IEEE
13 years 7 months ago
2007
IEEE
This paper presents an optimized design approach of two’s complement large-size squarers using embedded multipliers in FPGAs. The realization is based on BaughWooley’s algorit...
ASAP
2007
IEEE
13 years 7 months ago
2007
IEEE
Interconnect validation is an important early step toward global SoC (System-On-Chip) validation. Fast performances evaluation and design space exploration for NoCs (Networks-On-C...
ASAP
2007
IEEE
13 years 5 months ago
2007
IEEE
Commercial designs are integrating from 10 to 100 embedded functional and storage blocks in a single system on chip (SoC) currently, and the number is likely to increase significa...
WSC
2007
13 years 7 months ago
2007
We discuss SBatch, a simplified procedure for steady-state simulation analysis that is based on spaced batch means, incorporating many advantages of its predecessorsASAP3 and WAS...
ASAP
2007
IEEE
13 years 7 months ago
2007
IEEE
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...