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ASPDAC
2005
ACM
78views Hardware» more  ASPDAC 2005»
13 years 7 months ago
Timing driven track routing considering coupling capacitance
Abstract— As VLSI technology enters the ultra-deep submicron era, wire coupling capacitance starts to dominate self capacitance and can no longer be neglected in timing driven ro...
Di Wu, Jiang Hu, Min Zhao, Rabi N. Mahapatra
ASPDAC
2005
ACM
119views Hardware» more  ASPDAC 2005»
13 years 7 months ago
CMP aware shuttle mask floorplanning
- By putting different chips on the same mask, shuttle mask (or multiple project wafer) provides an economical solution for low volume designs and design prototypes to share the ri...
Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wo...
ASPDAC
2005
ACM
101views Hardware» more  ASPDAC 2005»
13 years 7 months ago
A wideband hierarchical circuit reduction for massively coupled interconnects
— We develop a realizable circuit reduction to generate the interconnect macro-model for parasitic estimation in wideband applications. The inductance is represented by VPEC (vec...
Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan
ASPDAC
2005
ACM
113views Hardware» more  ASPDAC 2005»
13 years 11 months ago
Scalable interprocedural register allocation for high level synthesis
Abstract— The success of classical high level synthesis has been limited by the complexity of the applications it can handle, typically not large enough to necessitate the depart...
Rami Beidas, Jianwen Zhu
ASPDAC
2005
ACM
65views Hardware» more  ASPDAC 2005»
13 years 11 months ago
Multilevel full-chip gridless routing considering optical proximity correction
To handle modern routing with nanometer effects, we need to consider designs of variable wire widths and spacings, for which gridless routers are desirable due to their great fle...
Tai-Chen Chen, Yao-Wen Chang