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ASPDAC
2009
ACM
262views Hardware» more  ASPDAC 2009»
13 years 11 months ago
Fault modeling and testing of retention flip-flops in low power designs
Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologie...
Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, ...
ASPDAC
2009
ACM
164views Hardware» more  ASPDAC 2009»
13 years 9 months ago
High-performance global routing with fast overflow reduction
Global routing is an important step for physical design. In this paper, we develop a new global router, NTUgr, that contains three major steps: prerouting, initial routing, and enh...
Huang-Yu Chen, Chin-Hsiung Hsu, Yao-Wen Chang
ASPDAC
2009
ACM
190views Hardware» more  ASPDAC 2009»
13 years 9 months ago
A reverse-encoding-based on-chip AHB bus tracer for efficient circular buffer utilization
The post-T/pre-T trace refers to the trace captured before/after a target point is reached, respectively. Real time compression of the post-T trace in a circular buffer is a challe...
Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang
ASPDAC
2009
ACM
141views Hardware» more  ASPDAC 2009»
13 years 9 months ago
Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri...
ASPDAC
2009
ACM
115views Hardware» more  ASPDAC 2009»
13 years 3 months ago
Frequent value compression in packet-based NoC architectures
The proliferation of Chip Multiprocessors (CMPs) has led to the integration of large on-chip caches. For scalability reasons, a large on-chip cache is often divided into smaller ba...
Ping Zhou, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, Ju...