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ASPDAC
2009
ACM

Fault modeling and testing of retention flip-flops in low power designs

11 years 6 months ago
Fault modeling and testing of retention flip-flops in low power designs
Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologies are not sufficient to test the retention flip-flop thoroughly. This paper presents four new fault models and the testing of retention flip-flop. The four fault models are awakemode stuck-at fault, sleep-mode stuck-at fault, awake-mode transition fault, and sleep-mode transition fault. The four faults model the defects that affect the retained value, wakeup time, and sleep time of retention flip-flops. Based on the new fault models, test patterns for retention flip-flop can be easily generated by current automatic test pattern generation tools. The proposed test methodology is validated by performing experiments on ISCAS’89 benchmark circuits and some realistic industrial low power designs. The experimental results show that the faults of retention flip-flops can be easily detected by our method and the av...
Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li,
Added 28 May 2010
Updated 28 May 2010
Type Conference
Year 2009
Where ASPDAC
Authors Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, Kun-Cheng Wu
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