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ATS
2004
IEEE
97views Hardware» more  ATS 2004»
13 years 8 months ago
Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores
TIS (Test Instruction Set) is an instruction level technique for CPU core self-testing. This method is based on enhancing a CPU instruction set with test instructions. TIS replace...
Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin N...
ATS
2004
IEEE
126views Hardware» more  ATS 2004»
13 years 8 months ago
Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumptio
Test data volume and scan power are two major concerns in SoC test. In this paper we present an alternative run-length coding method through scan chain reconfiguration to reduce b...
Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Ya...
ATS
2004
IEEE
109views Hardware» more  ATS 2004»
13 years 8 months ago
Reconfiguration for Enhanced ALternate Test (REALTest) of Analog Circuits
An efficient design for test methodology to increase the test yield of analog circuits is presented. It is assumed that the analog circuits are tested using alternate tests that r...
Ganesh Srinivasan, Shalabh Goyal, Abhijit Chatterj...
ATS
2004
IEEE
108views Hardware» more  ATS 2004»
13 years 8 months ago
Rapid and Energy-Efficient Testing for Embedded Cores
Conventional serial connection of internal scan chains brings the power and time penalty. A novel parallel core wrapper design (pCWD) approach is presented in this paper for reduc...
Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman ...
ICSE
2004
IEEE-ACM
14 years 5 months ago
Feature-Oriented Programming and the AHEAD Tool Suite
1 Feature Oriented Programming (FOP) is an emerging paradigm for application synthesis, analysis, and optimization. A target application is specified declaratively as a set of feat...
Don S. Batory