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ICCAD
2002
IEEE
146views Hardware» more  ICCAD 2002»
14 years 1 months ago
Test-model based hierarchical DFT synthesis
With increasing design sizes and adoption of System on a Chip (SoC) methodology, design synthesis and test automation tools are hitting capacity and performance bottlenecks. Curre...
Sanjay Ramnath, Frederic Neuveux, Mokhtar Hirech, ...
DFT
2002
IEEE
115views VLSI» more  DFT 2002»
13 years 9 months ago
Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis
IDDQ test loses its effectiveness for deep sub-micron chips since it cannot distinguish between faulty and fault-free currents. The concept of current ratios, in which the ratio o...
Sagar S. Sabade, D. M. H. Walker
DFT
2002
IEEE
117views VLSI» more  DFT 2002»
13 years 9 months ago
Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthe...
Ozgur Sinanoglu, Alex Orailoglu
DFT
2002
IEEE
103views VLSI» more  DFT 2002»
13 years 9 months ago
Input Ordering in Concurrent Checkers to Reduce Power Consumption
A novel approach for reducing power consumption in checkers used for concurrent error detection is presented. Spatial correlations between the outputs of the circuit that drives t...
Kartik Mohanram, Nur A. Touba