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DFT
2006
IEEE
82views VLSI» more  DFT 2006»
13 years 11 months ago
VLSI Implementation of a Fault-Tolerant Distributed Clock Generation
In this paper we will introduce a novel approach for the on-chip generation of a faulttolerant clock. We will motivate why it becomes more and more desirable to provide VLSI circu...
Markus Ferringer, Gottfried Fuchs, Andreas Steinin...
DFT
2006
IEEE
77views VLSI» more  DFT 2006»
13 years 11 months ago
Fault Tolerant Active Pixel Sensors in 0.18 and 0.35 Micron Technologies
A Fault Tolerant Active Pixel Sensor (FTAPS) has been designed and fabricated to correct for point defects that occur in CMOS image sensors both at manufacturing and over the life...
Michelle L. La Haye, Cory Jung, David Chen, Glenn ...
DFT
2006
IEEE
85views VLSI» more  DFT 2006»
13 years 8 months ago
Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects
With the recent development of nanoscale materials and assembly techniques, it is envisioned to build high-density reconfigurable systems which have never been achieved by the pho...
Yadunandana Yellambalase, Minsu Choi, Yong-Bin Kim
DELTA
2006
IEEE
13 years 11 months ago
Current Testable Design of Resistor String DACs
In this paper, supply current testability is examined experimentally for opens and shorts in a general 3 bit resistor string Digital/Analog converter(DAC). The results show that a...
Masaki Hashizume, Tomomi Nishida, Hiroyuki Yotsuya...
DFT
2006
IEEE
125views VLSI» more  DFT 2006»
13 years 11 months ago
Synthesis of Efficient Linear Test Pattern Generators
This paper presents a procedure for Synthesis of LINear test pattern Generators called SLING. SLING can synthesize linear test pattern generators that satisfy constraints on area,...
Avijit Dutta, Nur A. Touba