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DSD
2009
IEEE
118views Hardware» more  DSD 2009»
13 years 8 months ago
On the Risk of Fault Coupling over the Chip Substrate
—Duplication and comparison has proven to be an efficient method for error detection. Based on this generic principle dual core processor architectures with output comparison ar...
Peter Tummeltshammer, Andreas Steininger
DSD
2009
IEEE
144views Hardware» more  DSD 2009»
13 years 11 months ago
Composable Resource Sharing Based on Latency-Rate Servers
Abstract—Verification of application requirements is becoming a bottleneck in system-on-chip design, as the number of applications grows. Traditionally, the verification comple...
Benny Akesson, Andreas Hansson, Kees Goossens
DSD
2009
IEEE
118views Hardware» more  DSD 2009»
13 years 11 months ago
Internet-Router Buffered Crossbars Based on Networks on Chip
—The scalability and performance of the Internet depends critically on the performance of its packet switches. Current packet switches are based on single-hop crossbar fabrics, w...
Kees Goossens, Lotfi Mhamdi, Iria Varela Senin
DSD
2009
IEEE
84views Hardware» more  DSD 2009»
13 years 11 months ago
Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures
— 3D stacked architectures provide significant benefits in performance, footprint and yield. However, vertical stacking increases the thermal resistances, and exacerbates tempe...
Ayse Kivilcim Coskun, Andrew B. Kahng, Tajana Simu...
DSD
2009
IEEE
136views Hardware» more  DSD 2009»
13 years 8 months ago
An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload
Modern systems are able to put two or more processors on the same die (Chip Multiprocessors, CMP), each with its private caches, while the last level caches can be either private ...
Pierfrancesco Foglia, Francesco Panicucci, Cosimo ...