Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures

— 3D stacked architectures provide significant benefits in performance, footprint and yield. However, vertical stacking increases the thermal resistances, and exacerbates temperatureinduced problems that affect system reliability, performance, leakage power and cooling cost. In addition, the overhead due to through-silicon-vias (TSVs) and scribe lines contribute to the overall area, affecting wafer utilization and yield. As any of the aforementioned parameters can limit the 3D stacking process of a multiprocessor SoC (MPSoC), in this work we investigate the tradeoffs between cost and temperature profile across various technology nodes. We study how the manufacturing costs change when the number of layers, defect density, number of cores, and power consumption vary. For each design point, we also compute the steady state temperature profile, where we utilize temperature-aware floorplan optimization to eliminate the adverse effects of inefficient floorplan decisions on temperatu...

• Type: Conference
• Year: 2009
• Where: DSD
• Authors: Ayse Kivilcim Coskun, Andrew B. Kahng, Tajana Simunic Rosing
• Keywords: Design Point, Desirable Design Point, DSD 2009, Hardware, Temperature Profile