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    VLSISP
    1998
    128views more  VLSISP 1998»
    A Low Power DSP Engine for Wireless Communications
    13 years 4 months ago
    A Low Power DSP Engine for Wireless Communications
    Download  www.ee.ucla.edu
    This paper describes the architecture and the performance of a new programmable 16-bit Digital Signal Processor (DSP) engine. It is developed specifically for next generation wire...
    Ingrid Verbauwhede, Mihran Touriguian
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    TCAD
    1998
    159views more  TCAD 1998»
    Code density optimization for embedded DSP processors using data compression techniques
    13 years 4 months ago
    Code density optimization for embedded DSP processors using data compression techniques
    Download  reference.kfupm.edu.sa
    We address the problem of code size minimization in VLSI systems with embedded DSP processors. Reducing code size reduces the production cost of embedded systems. We use data comp...
    Stan Y. Liao, Srinivas Devadas, Kurt Keutzer
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    TVLSI
    2008
    133views more  TVLSI 2008»
    A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
    13 years 5 months ago
    A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
    Download  www.eecs.wsu.edu
    Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
    Mitchell J. Myjak, José G. Delgado-Frias
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    VLSISP
    2008
    100views more  VLSISP 2008»
    Memory-constrained Block Processing for DSP Software Optimization
    13 years 5 months ago
    Memory-constrained Block Processing for DSP Software Optimization
    Download  www.ece.umd.edu
    Digital signal processing (DSP) applications involve processing long streams of input data. It is important to take into account this form of processing when implementing embedded ...
    Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattach...
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    JPDC
    2008
    108views more  JPDC 2008»
    Energy minimization with loop fusion and multi-functional-unit scheduling for multidimensional DSP
    13 years 5 months ago
    Energy minimization with loop fusion and multi-functional-unit scheduling for multidimensional DSP
    Download  www.utdallas.edu
    Energy saving is becoming one of the major design issues in processor architectures with multiple functional units (FUs). Nested loops are usually the most critical part in multim...
    Meikang Qiu, Edwin Hsing-Mean Sha, Meilin Liu, Man...
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