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TVLSI
2010
13 years 13 days ago
Improving FPGA Performance for Carry-Save Arithmetic
The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP...
Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk,...
TPDS
2010
144views more  TPDS 2010»
13 years 4 months ago
Performance Evaluation of Dynamic Speculative Multithreading with the Cascadia Architecture
—Thread-level parallelism (TLP) has been extensively studied in order to overcome the limitations of exploiting instruction-level parallelism (ILP) on high-performance superscala...
David A. Zier, Ben Lee
MEMOCODE
2010
IEEE
13 years 3 months ago
Feldspar: A domain specific language for digital signal processing algorithms
A new language, Feldspar, is presented, enabling high-level and platform-independent description of digital signal processing (DSP) algorithms. Feldspar is a pure functional langua...
Emil Axelsson, Koen Claessen, Gergely Dévai...
BMCBI
2010
109views more  BMCBI 2010»
13 years 5 months ago
FPGA acceleration of the phylogenetic likelihood function for Bayesian MCMC inference methods
Background: Likelihood (ML)-based phylogenetic inference has become a popular method for estimating the evolutionary relationships among species based on genomic sequence data. Th...
Stephanie Zierke, Jason D. Bakos
DATE
2010
IEEE
140views Hardware» more  DATE 2010»
13 years 10 months ago
Construction of dual mode components for reconfiguration aware high-level synthesis
High-level synthesis has recently started to gain industrial acceptance, due to the improved quality of results and the multi-objective optimizations offered. One optimization area...
George Economakos, Sotirios Xydis, Ioannis Koutras...