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HPCA
2000
IEEE
11 years 4 months ago
eXtended Block Cache
This paper describes a new instruction-supply mechanism, called the eXtended Block Cache (XBC). The goal of the XBC is to improve on the Trace Cache (TC) hit rate, while providing...
Stéphan Jourdan, Lihu Rappoport, Yoav Almog...
MICRO
2010
IEEE
238views Hardware» more  MICRO 2010»
10 years 9 months ago
Sampling Dead Block Prediction for Last-Level Caches
Last-level caches (LLCs) are large structures with significant power requirements. They can be quite inefficient. On average, a cache block in a 2MB LRU-managed LLC is dead 86% of ...
Samira Manabi Khan, Yingying Tian, Daniel A. Jimen...
ISCA
2011
IEEE
290views Hardware» more  ISCA 2011»
10 years 3 months ago
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks
To meet the demand for more powerful high-performance shared-memory servers, multiprocessor systems must incorporate eļ¬ƒcient and scalable cache coherence protocols, such as thos...
Blas Cuesta, Alberto Ros, María Engracia G&...
ISCA
2011
IEEE
273views Hardware» more  ISCA 2011»
10 years 3 months ago
Bypass and insertion algorithms for exclusive last-level caches
Inclusive last-level caches (LLCs) waste precious silicon estate due to cross-level replication of cache blocks. As the industry moves toward cache hierarchies with larger inner l...
Jayesh Gaur, Mainak Chaudhuri, Sreenivas Subramone...
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