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EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
Clock routing has become a critical issue in the layout design of high-performance systems. We show that the two passes bottom-up and top-down of the DME algorithm 2, 3, 4, 8 can ...
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
System-levelpartitioning assigns functionalobjects such as tasks or code segments to system-level components such as o-the-shelf processors or application-speci c architectures in...
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
In this paper we introduce a new knowledgebased method for planning and managing the VLSI design process, based on prediction and advice, that minimizes search in a wide design sp...
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
of a direct implementation of this criterion. This paper presents the first critical path finding tool based on the exact criterion. It offers therefore better results in compariso...
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
This paper presents Resist, a recursive test pattern generation (TPG) algorithm for path delay fault testing of scan-based circuits. In contrast to other approaches, it exploits t...