RESIST: a recursive test pattern generation algorithm for path delay faults

This paper presents Resist, a recursive test pattern generation (TPG) algorithm for path delay fault testing of scan-based circuits. In contrast to other approaches, it exploits the fact that many paths in a circuit have common subpaths. Resist sensitizes those subpaths only once, reducing the number of value assignments during path sensitization signicantly. In addition, our procedure identies large sets of redundant path delay faults without enumerating them. Resist is capable of performing TPG for all path delay faults in all ISCAS-85 and ISCAS-89 circuits. For the rst time, results for all path delay faults in circuit c6288 are presented. A comparison with other TPG systems revealed that Resist is signicantly faster than all previously published methods.

• Type: Conference
• Year: 1994
• Where: EURODAC
• Authors: Karl Fuchs, Michael Pabst, Torsten Rössel
• Keywords: Delay Fault Testing, EURODAC 1994, Path Delay Faults, Redundant Path Delay, VHDL