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EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
Abstract -- A general framework for synthesis of asynchronous control circuits at the state graph level is proposed. The framework can consider both concurrency reduction as well a...
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
synchronisation also play a fundamental role in overall system robustness. ElectroMagnetic Compatibility (EMC) and ElectroMagnetic Interference (EMI) issues also have to be conside...
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
payload. The current recommendations include SDH as the physical layer transmission standard. It is defined the BISDN user network interface (UNI) SDH-based at 155.52 Mbit/s, but t...