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EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signi cantly a ect the actual...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
In order to extract a suitable common core information model, design representations on both system and architecture levels are analyzed. Following the specification trajectory, ...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
We present a system for the formal veri cation of processors which combines a computer algebra simpli cation tool with an object-oriented approach. It has been successfully used f...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
The presented fault model uniquely describes all structural changes in the transistor net list that can be caused by spot defects, including faults that connect more than two nets...