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11

EURODAC
1995
IEEE

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Quality considerations in delay fault testing

13 years 8 months ago

Quality considerations in delay fault testing

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We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signicantly aect the actual delays, but which are not taken into account by the existing models used in testing. Our analysis questions the test quality oered by test generation procedures used so far.

Alicja Pierzynska, Slawomir Pilarski

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Delay Models | EURODAC 1995 | Test Generation Procedures | VHDL | VLSI Circuit Testing |

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Added	26 Aug 2010
Updated	26 Aug 2010
Type	Conference
Year	1995
Where	EURODAC
Authors	Alicja Pierzynska, Slawomir Pilarski

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