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EURODAC
1995
IEEE

Quality considerations in delay fault testing

9 years 1 months ago
Quality considerations in delay fault testing
We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signi cantly a ect the actual delays, but which are not taken into account by the existing models used in testing. Our analysis questions the test quality o ered by test generation procedures used so far.
Alicja Pierzynska, Slawomir Pilarski
Added 26 Aug 2010
Updated 26 Aug 2010
Type Conference
Year 1995
Where EURODAC
Authors Alicja Pierzynska, Slawomir Pilarski
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