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ICCAD
2004
IEEE
125views Hardware» more  ICCAD 2004»
14 years 2 months ago
Temporal floorplanning using the T-tree formulation
Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and functionality. In this paper, we model each task ...
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
ESTIMEDIA
2004
Springer
13 years 11 months ago
A hardware accelerator IP for EBCOT Tier-1 coding in JPEG2000 Standard
We proposed a hardware accelerator IP for the Tier-1 portion of Embedded Block Coding with Optimal Truncation (EBCOT) used in the JPEG2000 next generation image compression standa...
Tien-Wei Hsieh, Youn-Long Lin
FPL
2004
Springer
103views Hardware» more  FPL 2004»
13 years 11 months ago
Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs
Abstract. Function evaluation is at the core of many compute-intensive applications which perform well on reconfigurable platforms. Yet, in order to implement function evaluation ...
Dong-U Lee, Oskar Mencer, David J. Pearce, Wayne L...
FPL
2004
Springer
125views Hardware» more  FPL 2004»
13 years 11 months ago
SoftSONIC: A Customisable Modular Platform for Video Applications
This paper presents the Customisable Modular Platform (CMP) approach. The aim is to accelerate FPGA application developraising the level of abstraction and facilitating design reus...
Tero Rissa, Peter Y. K. Cheung, Wayne Luk
ASPDAC
2004
ACM
218views Hardware» more  ASPDAC 2004»
13 years 9 months ago
A compressed frame buffer to reduce display power consumption in mobile systems
Abstract-- Despite the limited power available in a batteryoperated hand-held device, a display system must still have an enough resolution and sufficient color depth to deliver th...
Hojun Shim, Naehyuck Chang, Massoud Pedram