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GLVLSI
2005
IEEE
158views VLSI» more  GLVLSI 2005»
13 years 11 months ago
Quantum-dot cellular automata SPICE macro model
This paper describes a SPICE model development methodology for Quantum-Dot Cellular Automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simula...
Rui Tang, Fengming Zhang, Yong-Bin Kim
GLVLSI
2005
IEEE
205views VLSI» more  GLVLSI 2005»
13 years 11 months ago
Optimization objectives and models of variation for statistical gate sizing
This paper approaches statistical optimization by examining gate delay variation models and optimization objectives. Most previous work on statistical optimization has focused exc...
Matthew R. Guthaus, Natesan Venkateswaran, Vladimi...
GLVLSI
2005
IEEE
118views VLSI» more  GLVLSI 2005»
13 years 11 months ago
A continuous time markov decision process based on-chip buffer allocation methodology
We have presented an optimal on-chip buffer allocation and buffer insertion methodology which uses stochastic models of the architecture. This methodology uses finite buffer s...
Sankalp Kallakuri, Nattawut Thepayasuwan, Alex Dob...
GLVLSI
2005
IEEE
83views VLSI» more  GLVLSI 2005»
13 years 11 months ago
Diagnosing multiple transition faults in the absence of timing information
As timing requirements in today’s advanced VLSI designs become more aggressive, the need for automated tools to diagnose timing failures increases. This work presents two such a...
Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Ven...
GLVLSI
2005
IEEE
97views VLSI» more  GLVLSI 2005»
13 years 11 months ago
On equivalence checking and logic synthesis of circuits with a common specification
In this paper we develop a theory of equivalence checking (EC) and logic synthesis of circuits with a common specification (CS). We show that two combinational circuits N1, N2 have...
Eugene Goldberg