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GLVLSI
2010
IEEE
150views VLSI» more  GLVLSI 2010»
13 years 7 months ago
Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS
Transistor aging effects (NBTI and PBTI) impact the reliability of SRAM in nano-scale CMOS technologies. In this research, the combined effect of NBTI and PBTI on power gated SRAM...
Anuj Pushkarna, Hamid Mahmoodi
GLVLSI
2010
IEEE
189views VLSI» more  GLVLSI 2010»
13 years 10 months ago
8Gb/s capacitive low power and high speed 4-PWAM transceiver design
In this paper, capacitive 4-PWAM transmitter architectures and circuits are proposed and its performances are analyzed with random jitter and PVT variation comparing with other wo...
Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi
GLVLSI
2010
IEEE
139views VLSI» more  GLVLSI 2010»
13 years 10 months ago
Dynamically resizable binary decision diagrams
We present the architecture of a new Ordered Binary Decision Diagram library that is designed from the ground up to be space efficient. The main novelty lies in the library’s no...
Stergios Stergiou, Jawahar Jain
GLVLSI
2010
IEEE
138views VLSI» more  GLVLSI 2010»
13 years 10 months ago
Methodology to achieve higher tolerance to delay variations in synchronous circuits
A methodology is proposed for designing robust circuits exhibiting higher tolerance to process and environmental variations. This higher tolerance is achieved by exploiting the in...
Emre Salman, Eby G. Friedman
GLVLSI
2010
IEEE
296views VLSI» more  GLVLSI 2010»
13 years 5 months ago
AOP-based high-level power estimation in SystemC
The paper presents a novel high-level power modeling and estimation framework. The approach is based on a synergic integration of aspect-oriented programming(AOP) and SystemC. Mac...
Feng Liu, QingPing Tan, Xiaoyu Song, Naeem Abbasi