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IEEEPACT
2000
IEEE
13 years 9 months ago
aSOC: A Scalable, Single-Chip Communications Architecture
As on-chip integration matures, single-chip system designers must not only be concerned with component-level issues such as performance and power, but also with onchip system-leve...
Jian Liang, Sriram Swaminathan, Russell Tessier
IEEEPACT
2000
IEEE
13 years 9 months ago
Neighborhood Prefetching on Multiprocessors Using Instruction History
A multiprocessor prefetch scheme is described in which a miss is followed by a prefetch of a group of lines, a neighborhood, surrounding the demand-fetched line. The neighborhood ...
David M. Koppelman
IEEEPACT
2000
IEEE
13 years 9 months ago
Global Register Partitioning
Modern computers have taken advantage of the instruction-level parallelism (ILP) available in programs with advances in both architecture and compiler design. Unfortunately, large...
Jason Hiser, Steve Carr, Philip H. Sweany
IEEEPACT
2007
IEEE
13 years 11 months ago
Component-Based Lock Allocation
The allocation of lock objects to critical sections in concurrent programs affects both performance and correctness. Recent work explores automatic lock allocation, aiming primari...
Richard L. Halpert, Christopher J. F. Pickett, Cla...
IEEEPACT
2005
IEEE
13 years 11 months ago
Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors
This paper proposes a new hardware technique for using one core of a CMP to prefetch data for a thread running on another core. Our approach simply executes a copy of all non-cont...
Ilya Ganusov, Martin Burtscher