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CAINE
2003
13 years 7 months ago
An Issue Logic for Superscalar Microprocessors
In order to enhance the computer performance, nowadays microprocessors use Superscalar architecture. But the Superscalar architecture is unable to enhance the performance effectiv...
Feng-Jiann Shiao, Jong-Jiann Shieh
PDPTA
2003
13 years 7 months ago
Comparing Multiported Cache Schemes
The performance of the data memory hierarchy is extremely important in current and near future high performance superscalar microprocessors. To address the memory gap, computer de...
Smaïl Niar, Lieven Eeckhout, Koenraad De Boss...
ENTCS
2007
78views more  ENTCS 2007»
13 years 5 months ago
PEPA Queues: Capturing Customer Behaviour in Queueing Networks
Queueing network formalisms are very good at describing the spatial movement of customers, but typically poor at describing how customers change as they move through the network. ...
Ashok Argent-Katwala, Jeremy T. Bradley
ISCAPDCS
2004
13 years 7 months ago
One-Level Cache Memory Design for Scalable SMT Architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
Muhamed F. Mudawar, John R. Wani
VLSID
2007
IEEE
146views VLSI» more  VLSID 2007»
14 years 6 months ago
Architecting Microprocessor Components in 3D Design Space
Interconnect is one of the major concerns in current and future microprocessor designs from both performance and power consumption perspective. The emergence of three-dimensional ...
Balaji Vaidyanathan, Wei-Lun Hung, Feng Wang 0004,...