An Issue Logic for Superscalar Microprocessors

In order to enhance the computer performance, nowadays microprocessors use Superscalar architecture. But the Superscalar architecture is unable to enhance the performance effectively due to two reasons. One reason is the complexity design will reduce the clock frequency seriously and another reason is data dependency makes the instructions parallelism unable to break through the dataflow limitation. In this paper, we propose speculative wakeup logic to enhance the instructions parallelism. In order to issue more instructions every cycle, an issue table is added to help the select logic select the suitable instructions to issue. Simulation results show the average IPC is increased by 22.5% in SPECInt and 45% in SPECfp over a conventional architecture.

• Type: Conference
• Year: 2003
• Where: CAINE
• Authors: Feng-Jiann Shiao, Jong-Jiann Shieh
• Keywords: CAINE 2003, CAINE 2007, Instructions Parallelism, Speculative Wakeup Logic, Superscalar Architecture