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    1998
    IEEE
    74views Hardware» more  DATE 1998»
    State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits
    13 years 9 months ago
    State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits
    Download  computing.ece.vt.edu
    We extend the subsequence removal technique to provide signi cantly higher static compaction for sequential circuits. We show that state relaxation techniques can be used to ident...
    Michael S. Hsiao, Srimat T. Chakradhar
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    CP
    1998
    Springer
    110views Artificial Intelligence» more  CP 1998»
    Generation of Test Patterns for Differential Diagnosis of Digital Circuits
    13 years 9 months ago
    Generation of Test Patterns for Differential Diagnosis of Digital Circuits
    Download  ssdi.di.fct.unl.pt
    In a faulty digital circuit, many (single) faulty gates may explain the observed findings. In this paper we are mostly concerned, not in obtaining alternative diagnoses, but rathe...
    Francisco Azevedo, Pedro Barahona
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    IJFCS
    1998
    67views more  IJFCS 1998»
    Vertex Splitting in Dags and Applications to Partial Scan Designs and Lossy Circuits
    13 years 5 months ago
    Vertex Splitting in Dags and Applications to Partial Scan Designs and Lossy Circuits
    Download  www.cise.ufl.edu
    Directed acyclic graphs (dags) are often used to model circuits. Path lengths in such dags represent circuit delays. In the vertex splitting problem, the objective is to determine...
    Doowon Paik, Sudhakar M. Reddy, Sartaj Sahni
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    TCAD
    1998
    82views more  TCAD 1998»
    LOT: Logic Optimization with Testability. New transformations for logic synthesis
    13 years 5 months ago
    LOT: Logic Optimization with Testability. New transformations for logic synthesis
    Download  www-eda.eit.uni-kl.de
    —A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random...
    Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang K...
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    TCAD
    1998
    91views more  TCAD 1998»
    Cost-free scan: a low-overhead scan path design
    13 years 5 months ago
    Cost-free scan: a low-overhead scan path design
    Download  www.cecs.uci.edu
    Conventional scan design imposes considerable area and delay overhead by using larger scan ip- ops and additional scan wires without utilizing the functionality of the combinatio...
    Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Ti...
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