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ISCA
2009
IEEE
137views Hardware» more  ISCA 2009»
14 years 8 days ago
A case for an interleaving constrained shared-memory multi-processor
Shared-memory multi-threaded programming is inherently more difficult than single-threaded programming. The main source of complexity is that, the threads of an application can in...
Jie Yu, Satish Narayanasamy
ISCA
2009
IEEE
178views Hardware» more  ISCA 2009»
14 years 8 days ago
Thread motion: fine-grained power management for multi-core systems
Dynamic voltage and frequency scaling (DVFS) is a commonly-used powermanagement scheme that dynamically adjusts power and performance to the time-varying needs of running programs...
Krishna K. Rangan, Gu-Yeon Wei, David Brooks
VLSID
2009
IEEE
87views VLSI» more  VLSID 2009»
14 years 6 months ago
Soft Error Rates with Inertial and Logical Masking
We analyze the neutron induced soft error rate (SER). An induced error pulse is modeled by two parameters, probability of occurrence and probability density function of the pulse ...
Fan Wang, Vishwani D. Agrawal
CATA
2009
13 years 6 months ago
Impact of Computing on the World Economy: A Position Paper
As computing technologies continue to rapidly advance since the last two decades, the knowledge economy has become an important part of the overall world economy. In addition to i...
Frederick Harris, Gordon K. Lee, Stuart Harvey Rub...
ISCA
2009
IEEE
138views Hardware» more  ISCA 2009»
14 years 8 days ago
Achieving predictable performance through better memory controller placement in many-core CMPs
In the near term, Moore’s law will continue to provide an increasing number of transistors and therefore an increasing number of on-chip cores. Limited pin bandwidth prevents th...
Dennis Abts, Natalie D. Enright Jerger, John Kim, ...